Matteo Silotto

U-BOOT hang after LPDDR4 calibration timing update

Discussion created by Matteo Silotto on Jul 21, 2020
Latest reply on Jul 22, 2020 by Wigros Sun



I'm working on a custom design with the i.MX8M Mini processor.
I successfully completed the RAM calibration process on many boards, and I'm working to integrate the new values on U-Boot lpddr4_timing.c source file.


I have updated all the values obtained from the DDR calibration tool, exept for the following two entry:


   { 0x3d4020f4, 0xc99 }
   { 0x3d4030f4, 0xc99 }


When I add these two values on lpddr4_timing.c the U-Boot SPL hangs after the DRAM init procedure.

On the original lpddr4_timing.c source file these two registers are not listed (unlike all other registers that are already present).


I can't find on the reference manual any information about these.


Please help me to know the meaning of these registers and if they need to be updated for the correct integration of calibration results.



Best regards,