My target is S32K148,
I'm doing DMA on LPSPI,
There's something that I can't justify :
DONE bit in the TDR DMA channels for RX/TX don't get set simultaneously whereas I think they should .
When the transfer is complete that means all the data on MOSI,and MISO has been transferred .
I'm under the impression when the major loop has completed its count the transfer is complete.
But my observation is that they are out of phase , when one is set the other is cleared and visa versa.
I assigned same priority of 0 to both channel.
Is this a normal behavior ? or there's something going on.
Please educate me.