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Adding an amplifier to i.MX8QuadMax

Question asked by Yavuz Selim Mutlu on Feb 21, 2020
Latest reply on Feb 27, 2020 by igorpadykov

Hi all,

 

I am trying to add a D class amplifier using esai0, using the simple-audio-card driver and custom codec tas6424.

Firstly, I implemented the i2c interface for codec driver to i2c0_cm41 which is:

 tas6424: tas6424@6a {
      compatible = "ti,tas6424";
      reg = <0x6a>;
      #sound-dai-cells = <0>;
      standby-gpios = <&gpio3 5 GPIO_ACTIVE_LOW>;
      mute-gpios = <&gpio3 27 GPIO_ACTIVE_LOW>;
};

 

Then, I added simple-card-audio device tree binding as:

sound-ti-d-class {
        compatible = "simple-audio-card";
        simple-audio-card,name = "TI-D-Class-Amplifier";
        simple-audio-card,mclk-fs = <128>;
        simple-audio-card,format = "i2s";
        simple-audio-card,cpu {
                 sound-dai = <&esai0>;

        };
        simple-audio-card,codec {
                sound-dai = <&tas6424>;

        };       
    };

After doing these, I can see the card by aplay -l as:

card 3: TIDClassAmplifi [TI-D-Class-Amplifier], device 0: 59010000.esai-tas6424-amplifier tas6424-amplifier-0 []
Subdevices: 1/1
Subdevice #0: subdevice #0

and, I can see snd_controls in the alsamixer and able to change these controls.

 

However, it constantly gives an error:

[ 461.093818] fsl-esai-dai 59010000.esai: failed to derive required HCKT rate
[ 461.100909] asoc-simple-card sound-ti-d-class: ASoC: machine hw_params failed: -22

 

I examined the fsl_esai.c driver, I concluded that there is a problem with the clock rates. In the amplifier datasheet the clock rates explained as:

     The device supports MCLK rates of 128 × fS , 256 × fS , or 512 × fS .
     The device supports SCLK rates of 32 × f S , 48 × f S or 64 × f S .
     The device supports FSYNC rates of 44.1 kHz, 48 kHz, or 96 kHz.
     The maximum clock frequency is 25 MHz. Therefore, for a 96-kHz FSYNC rate, the maximum MCLK rate is
          256 × fS .
     The MCLK clock must not be in phase to sync to SCLK. Duty cycle of 50% is required for 128x FSYNC, for 256x
         and 512x 50% duty is not required.

 

How can I set the correct clock rates for the esai interface? I think esai documentation is not mature enough to explain these situations clearly. Is there any comment about this subject?

 

In case you wonder, the BSP is Linux 4.14.98.

&esai0 {     
    compatible = "fsl,imx8qm-esai";     
    pinctrl-names = "default";     
    pinctrl-0 = <&pinctrl_esai0>;     
    assigned-clocks = <&clk IMX8QM_ACM_ESAI0_MCLK_SEL>,             
    <&clk IMX8QM_AUD_PLL0_DIV>,             
    <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK0_DIV>,             
    <&clk IMX8QM_AUD_ACM_AUD_REC_CLK0_DIV>,             
    <&clk IMX8QM_AUD_ESAI_0_EXTAL_IPG>;     
    assigned-clock-parents = <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK0_CLK>;     
    assigned-clock-rates = <0>, <786432000>, <49152000>, <12288000>, <49152000>;     
    fsl,txm-rxs;     
    status = "okay";
};

 

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