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ECSPI multibyte transfer without CS toggle

Question asked by Michael Stahl on Feb 13, 2020
Latest reply on Feb 25, 2020 by Artur Petukhov


I use a ECSPI on an i.MX6q processor. Attachet to this SPI Master is a FRAM. The SPI itself runs (SCLK, MISO, MOSI) and also the CS. But the CS doesn't work how I expect it.


I use 8 bit per transfer and do my communication by ioctl from userspace. The FRAM works with the rohm,dh2228fv driver which is based on the spidev driver.


To read for exmple the FRAM's ID I have to send a command byte and additionally read three data bytes. The CS should stay low during the whole sequence.

What happen is that the CS goes high after every byte. This causes that I am not able to read the FRAM's ID because a rising edge abort the communication.

I tried to use the cs_change property of the spi_ioc_transfer struct but without sucess.


If I configure the CS pin as normal GPIO and control it myself over the sysfs everything is well. But I am not satisfied with this because it take a long time to set/unset the CS-pin.


I found a patch for the spi-imx.c from 2013 but I can't see that this patch is in the current version of spi-imx.c.