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800x480 HDMI support on iMX8MQ

Question asked by Nico Coesel on Apr 28, 2019
Latest reply on Jun 11, 2019 by Nico Coesel

I have an 800x480 HDMI display but it doesn't work on the iMX8MQEVK. I get the following console output:

[  221.421192] [drm] HDMI/DP Cable Plug In
[  221.436809] i.mx8-hdp 32c00000.hdmi: 0,ff,ff,ff,ff,ff,ff,0
[  221.450672] [drm] Link rate is too high - forcing link to lower rate
[  221.457202] [drm] Pixel clock frequency: 172780 KHz, character clock frequency: 172780, color depth is 8-bit.
[  221.467385] [drm] Pixel clock frequency (172780 KHz) not supported for this color depth (8-bit)
[  221.476375] [drm:hdmi_phy_init_t28hpc] *ERROR* failed to set phy pclock
[  221.483143] [drm:imx_hdp_mode_setup] *ERROR* Failed to initialise HDP PHY
[  221.493894] dcss-core 32e00000.dcss: Configured video pll 2 with ref_clk 2 freq 172780000 (actual 172799998)
[  221.503829] dcss-core 32e00000.dcss: pixel clock set to 172799998 Hz instead of 172780000 Hz, error is 19998 Hz

When enabling the debugging on DRM I see the following in the DMESG output:

[  221.421192] [drm] HDMI/DP Cable Plug In
[  221.424751] [drm:drm_ioctl] pid=3257, dev=0xe201, auth=1, DRM_IOCTL_MODE_GETRESOURCES
[  221.424763] [drm:drm_mode_object_put] OBJ ID: 46 (4)
[  221.424774] [drm:drm_ioctl] pid=3257, dev=0xe201, auth=1, DRM_IOCTL_MODE_GETRESOURCES
[  221.424781] [drm:drm_mode_object_put] OBJ ID: 46 (4)
[  221.424794] [drm:drm_ioctl] pid=3257, dev=0xe201, auth=1, DRM_IOCTL_MODE_GETCONNECTOR
[  221.436809] i.mx8-hdp 32c00000.hdmi: 0,ff,ff,ff,ff,ff,ff,0
[  221.442407] [drm:imx_hdp_connector_mode_valid] pixel clock 32000 out of range
[  221.442412] [drm:imx_hdp_connector_mode_valid] pixel clock 172780 out of range
[  221.442421] [drm:drm_mode_object_put] OBJ ID: 46 (4)
[  221.442431] [drm:drm_ioctl] pid=3257, dev=0xe201, auth=1, DRM_IOCTL_MODE_GETCONNECTOR
[  221.442439] [drm:drm_mode_object_put] OBJ ID: 46 (4)
[  221.442450] [drm:drm_ioctl] pid=3257, dev=0xe201, auth=1, DRM_IOCTL_MODE_OBJ_GETPROPERTIES

The pixel clock of 32MHz (32000kHz) is correct for an 800x480 @60Hz display so the EDID data seems to be interpreted correctly however it appears there is a limit on the pixel clock. How can this be fixed?

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