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Layout Design Guide Line for LPDDR4 on i.MX8QX

Question asked by Yoshihiro Tanno on Feb 4, 2019
Latest reply on Jul 29, 2019 by Sergey Serg
Branched to a new discussion


Now, we are designing our evaluation board circuit using iMX8QX.
So we want to know the following specification for LPDDR4 Layout Design Guide Line.

1.Line Length Difference (Differential Pair P/N, CK/DQS)
2.Line Length Difference (Single - ended, CS/CKE/DMI/CA/DQ)
3.Space between Differential Pair and Other Traces
   - CK_t/c to CAx, CS_n
   - CK_t/c to CKEx
   - CK_t/c to DQSx_t/c
   - DQS_t/c to DQ
   - DMI to DQ
4.Characteristic Impedance (Z0)
5.Differential Impedance (Z0_diff)

Thanks a lot