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FLEXCAN register vs. Supervisor-User-Secure-Non-Secure

Question asked by davide ponzetti on Jan 11, 2018
Latest reply on Jan 18, 2018 by igorpadykov

Hi all, pls, I'm working on an iMX6Q platform and when I try to read the FLEXCAN memory map (the MCR register  209_0000 instead the CTRL register 209_0004...) the system generate an exception. From what I read in datasheet "The access type can be Supervisor (S) or Unrestricted (U). Most of the registers can be configured to have either Supervisor or Unrestricted access by programming the SUPV bit in the MCR Register. The MCR register allows only
Supervisor access regardless the SUPV bit state" therefore I need to switch in Supervisor Secure Mode by the CSU_CSLx registers. There registers control teh access for each peripheral.

 

for additional clarification also in the FLEXCAN chapter is wroten "SUPV bit configures some of the FLEXCAN registers to be either in Supervisor or User Mode. Reset value of this bit is '1', so the affected registers start with Supervisor access allowance only. This bit can only be written in Freeze mode as it is blocked by hardware in other modes.
1 FlexCAN is in Supervisor Mode. Affected registers allow only Supervisor access.

!!!! Unrestricted access behaves as though the access was done to an unimplemented register location !!!!
0 FlexCAN is in User Mode. Affected registers allow both Supervisor and Unrestricted accesses"

 

Currently the CSU_CSL0 at 021c:0000 and CSU_CSL1 at 021c:0004 are 00330033 that means Supervisor and User Secure Only while I need to force them at 00FF0033 and 003300FF respectively.

I need to find the sentences to punt in the Device Tree customization ... DTB

 

Does anybody pls hepl me in that item?

 

Tks for all your time and attention.

Best Regards, Davide

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