We plan to use Cypress S70FS01GS QSPI Nor flash in our QorIQ LS1043A based design. The flash size is 128MB (1Gb). The flash is two die stacked (two FS512S, 64MB each), but with only one CS (chip select) to emulate one die, hence I think the two die support in LS1043A does not apply. The emulation of one die in the flash is not 100%, especially sequential read is tricky, because it's impossible to cross die boundary by sequential read: if a sequential read reach the maximum address of the first die (64MB), it continues reading from the very fist byte (of the first die).
When we read for example linux QSPI driver for Freescale QUADSPI (drivers/mtd/spi-nor/fsl-quadspi.c), we see the AHB buffer size is (read size, QSPI_BUFxCR[ADATSZ]) 1024 bytes (yes, only 8 bytes due to A-009282 for LS1043A, but let's forget the A-009282 for a while).
The natural question related to this observation is if the 1024 bytes read from the flash can cross the chip boundary in the specific scenario with the Cypress S70FS01GS.
Is the read from QSPI flash somehow aligned with respect to the AHB buffer size?
For example, if the ARM core loads 4 bytes from memory to register (by means of some load instruction) and the load address is QSPI_AMBA_BASE + 512 (load bytes from flash addresses 512, 513, 514 and 515 to the CPU register) and it is a "missed" access, which data (addresses) will be read from the flash? I see two basic possibilities:
- "aligned access" - read from flash address 0 to 1023
- "non-aligned access" - read from flash address 512 to 1535 (512 + 1023)
Moreover, there is the A-009282, to the AHB buffer size is only 8 bytes for LS1043A, but the situations seems to be the same in principle.