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i.MX Processors

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iWave systems recently launched a new SMARC System on Module (SOM) based on the powerful NXP i.MX 8QuadMax applications processors. This high performance SOM features an intelligent blend of MPUs+MCU power in a single device and integrates heterogeneous multicore 64 bit ARM processors (Dual Cortex A72@ 1.8 GHz + Quad Cortex A53 @ 1.2 GHz and Dual Cortex -M4F @ 266 MHz), targeted for applications that demand advanced real-time processing, multi-media performance as well as in applications that requires simultaneous multi-OS operations. For more details refer to the link: i.MX8 QuadMax NXP SMARC SOM

i.MX8 QM SOM

The Cortex M4F microcontroller plays an integral part in realizing various real-time operations of the SOM module. It is a powerful energy-efficient microcontroller core with floating-point arithmetic functionality that offers a low-latency execution environment with real-time and low-power processing capability running bare-metal code or a real-time operating system like FreeRTOS.

 

The Cortex ‑M4F microcontroller incorporates the following key features:

  • A processor core.
  • A Nested Vectored Interrupt Controller for low-latency interrupt processing.
  • Multiple high-performance bus interfaces.
  • Memory Protection Unit(MPU) & Floating Point Unit (FPU).
  • LPIT (Low-power Periodic Interrupt Timer) for periodic timer services
  • TPM (Timer PWM Module) for timer and PWM services
  • RGPIO (Rapid General-Purpose Input/Output) for the fast pin I/O capability
  • MU (Messaging Unit) for interprocessor communication
  • INT MUX (Interrupt Mux) to select local interrupts routed outside of the subsystem
  • SEMA42 (hardware semaphore) for HMP synchronization to shared resources
  • LPI2C (Low-Power I2C) for serial communication
  • LPUART (Low-Power UART) for serial communication and debug 

 

Optimized performance and efficiency for real-time processing:

To optimize performance and increase system efficiency it is always effective to separate computation tasks between various Cortex   cores. The Cortex A cores runs high-level OS (Linux /Android) and can be used to drive applications that demand compute-intensive graphics (2D/3D), 4K video, high speed data processing etc., while real-time applications such as sensor monitoring, data acquisition, motor control, etc., requires high degree of determinism and DSP capability which can be handled very efficiently by the RTOS running on the Cortex M4F cores. In addition, the SOM supports simultaneous operation of multiple OS platforms that enables the cores to drive totally independent applications, for e.g. When the Cortex A cores handle a system for HMI or an instrument cluster, the Cortex M4F can drive the circuitry for sensor control while utilizing RPC for interprocessor communications.

 

High-speed data acquisition:

On applications that make use of high-speed RF synthesis (ADC conversion), the Cortex -M4F core can be employed to acquire analog inputs at a high sample rate and offload the Cortex  A cores for instantaneous processing of the acquired data. For instance, in the case of industrial automation, where devices are often deployed in remote locations, the Cortex -M4F core continuously monitors various sensor operations and can instantly detect any signal variations and communicates it with Cortex A cores for instantaneous processing of the acquired data.

 

Intelligent power management:

In applications where the Cortex A cores waits for communication from the Cortex M4F cores, the system can take control of the situation and power gate the Cortex A cores. The Cortex A cores can go to sleep mode and can be activated either using predefined wake-up time or when there is a user-defined interrupt generated by Cortex M4F core. While the Cortex A core is shut down, the Cortex M4F continues to monitor the system in low power, thereby optimizing the power intakes.

 

Rear-view camera application using the Cortex M4F of i.MX8QM SMARC SOM

i.MX8 QM Development Platform

iWave Systems have validated the real-time performance of i.MX8QM SOM by demonstrating an application for the rear-view camera using only the Cortex M4F of the SOM. The application demonstrates the fast boot capability of the Cortex M4F  which is interfaced with the camera sensors mounted at the rear of the vehicle. After powering on the board in just 3 secs camera application starts to run. Cortex M4F acquires data from the camera sensors and displays the image/video on the rear-view mirror thereby aiding the users to reverse park their vehicles with ease.

 

Likewise, several industrial applications ranging from Automation, Drones, HMI, and High-End signage, both real-time and non-real time can be easily enabled using iWave’s powerful i.MX8QM SMARC SOM platform.

With 10+ years longevity, custom SOM configuration and dedicated technical support including carrier board review, software support, etc., designers and OEMs can be assured of iWave’s unwavering quality and long-term service. Our support resources include detailed hardware and software user manual, carrier board schematics, BSP package with toolchain support, reference designs, etc.,

 

For further information or inquiries please write to mktg@iwavesystems.com or contact our Regional Partners.

iWave Systems, a leading embedded solutions provider company based in Bangalore has successfully demonstrated Xen virtualization hypervisor on their i.MX8 QM SoC based System on Module. The  multi-core SOM comprises of 2x Arm Cortex -A72 @1.8 GHz and 4x Arm Cortex-A53 @1.2 GHz and 2x additional Cortex-M4F @ 266 MHz, rendering a highly powerful  integrated solution on a SMARC R2.0 compatible module.

i.MX8 QuadMax SMARC SOM                                                                          i.MX8 QM SMARC SOM

To fully explore the enormous computing capability of the i.MX8 QM SOM, iWave has implemented virtualization of hardware using the open source type 1 Xen hypervisor. The Xen hypervisor enables multiple virtual machines to be created over a single hardware resource, each virtual machine capable of running its own independent operating system. This enables the i.MX8 QM SOM run multiple operating systems concurrently on the same physical board. The Xen hypervisor allows maximum utilization of resources thereby improving overall system performance and efficiency.

About Xen hypervisor

Xen is an open source type-1 hypervisor developed by the University of Cambridge and is now being developed by the Linux Foundation. Xen runs directly on the hardware to manage guest operating systems. Hence, it's also considered as a bare metal hypervisor. Xen has less overhead enabling faster performance and Operating Systems are more secure as they don't rely on base OS for installing the hypervisor.

A system running the Xen hypervisor contains three components:

  • Xen Hypervisor
  • Domain 0 (Dom0) – Privileged virtual machine running on the hypervisor that can access the hardware directly and interact with other unprivileged virtual machine running on the system.
  • Multiple DomainU (DomU) – Unprivileged virtual machine running on the hypervisor and have no direct access to hardware (e.g. CPU,memory, timer and interrupts cannot be directly accessed)
 

During the initial system start-up, Xen hypervisor launches the Dom0 that runs the Linux operating system. The Dom0 has unique privileges to access the Xen hypervisor compared to other Domains. Dom0 manages the DomU, the unprivileged domains running on the system. Dom0 allocate and map hardware resources for the DomU domains.

Advantages: -

  • Less overhead compared to type-2 hypervisors since type-1 hypervisors make use of ARM virtualization extensions.
  • Having faulty/buggy OS in DOM-U domain will not disrupt the functionalities of DOM-0 OS.
  • DOM-U driver domains can support legacy hardware drivers no longer supported by new OS.
  • Have completely isolated workspaces with different requirements. Eg: gaming and multimedia.
  • Better resource management since resources rarely used will not be powered on if the domain it belongs to is not booted.
 

Xen demo on iWave’s i.MX8QM SOM

In iWave’s Xen Demo on i.MX8QM Board, the DOM-0 OS runs Linux 4.14.98 from eMMC and DOM-U runs Android Pie 9.0 from USB drives. Such a system can be used where there is a need for both faster, highly reliable OS (such as Linux) and more multi featured slightly slower OS (such as Android) to be running on the same hardware.

For further information or enquiries please write to mktg@iwavesystems.com.

GmSSL is an open source cryptographic toolbox that supports SM2 / SM3 / SM4 / SM9 and other national secret (national commercial password) algorithm, SM2 digital certificate and SM2 certificate based on SSL / TLS secure communication protocol to support the national security hardware password device , To provide in line with the national standard programming interface and command line tools, can be used to build PKI / CA, secure communication, data encryption and other standards in line with national security applications. For more information, please access GmSSL official website http://gmssl.org/english.html.

 

Software environments as the belows:

Linux kernel: imx_4.14.98_2.0.0_ga

cryptodev: 1.9

HW platform: i.MX6UL, i.MX7D/S, i.MX8M/MM, i.MX8QM/QXP.

The patches include the following features:

1, Support SM2/SM9 encryption/decryption/sign/verify/key exchange, RSA encryption/decryption, DSA/ECDSA sign/verify, DH/ECDH key agreement, ECC & DLC & RSA key generation and big number operation and elliptic curve math by CAAM hardware accelerating.

2, run "git apply 0001-Enhance-cryptodev-and-its-engine-in-GmSSL-by-CAAM-s-.patch" under folder sources/poky, and "git apply 0001-Add-public-key-cryptography-operations-in-CAAM-drive.patch" under folder sources/meta-fsl-bsp-release for patch these codes.

3, GmSSL Build command:

$ tar zxvf GmSSL-master-iMX.tgz

cd GmSSL-master-iMX

(For i.MX8M/MM, i.MX8QM/QXP)

source /opt/arm-arch64/environment-setup-aarch64-poky-linux 

$ ./Configure -DHAVE_CRYPTODEV -DUSE_CRYPTODEV_DIGESTS -DHW_ENDIAN_SWAP  --prefix=~/install64 --openssldir=/etc/gmssl --libdir=/usr/lib no-saf no-sdf no-skf no-sof no-zuc -no-ssl3 shared linux-aarch64

$ make 

$ make install                            /*image and config file will be installed to folder ~/install64 */

 

(For i.MX6UL, i.MX7D/S)

$ source /opt/arm-arch32/environment-setup-cortexa7hf-neon-poky-linux-gnueabi

$ ./Configure -DHAVE_CRYPTODEV -DUSE_CRYPTODEV_DIGESTS --prefix=~/install32 --openssldir=/etc/gmssl --libdir=/usr/lib no-saf no-sdf no-skf no-sof no-zuc -no-ssl3 shared linux-armv4

$ make 

$ make install                            /*image and config file will be installed to folder ~/install32 */

 

4, How to use GmSSL:

copy image gmssl to /usr/bin on i.MX board; copy gmssl libcrypto.so.1.1 and libssl.so.1.1 to /usr/lib on i.MX board; copy folder etc/gmssl to /etc/ on i.MX board. copy test examples (dhtest, dsatest, rsa_test, ecdhtest, ecdsatest, eciestest, sm3test, sms4test, sm2test, sm9test) under GmSSL-master-iMX/test  to U disk for running.

You can run test examples by the following commands:

#insmod /lib/modules/4.14.98-imx_4.14.98_2.0.0_ga+g5d6cbeafb80c/extra/cryptodev.ko

#/run/media/sda1/dhtest
#/run/media/sda1/dsatest
#/run/media/sda1/rsa_test
#/run/media/sda1/ecdhtest
#/run/media/sda1/ecdsatest
#/run/media/sda1/eciestest
#/run/media/sda1/sm3test
#/run/media/sda1/sms4test
#/run/media/sda1/sm2test
#/run/media/sda1/sm9test

and speed test commands:

#gmssl speed sm2
#gmssl genrsa -rand -f4 512
#gmssl speed dsa
#gmssl genrsa -rand -f4 1024
#gmssl speed rsa
#gmssl genrsa -rand -f4 2048
#gmssl speed ecdsa
#gmssl genrsa -rand -f4 3072
#gmssl speed ecdh
#gmssl genrsa -rand -f4 4096

GmSSL是一个开源的密码工具箱,支持SM2/SM3/SM4/SM9/ZUC等国密(国家商用密码)算法、SM2国密数字证书及基于SM2证书的SSL/TLS安全通信协议,提供符合国密规范的编程接口与命令行工具,可以用于构建PKI/CA、安全通信、数据加密等符合国密标准的安全应用。GmSSL项目是OpenSSL项目的分支,并与OpenSSL保持接口兼容。因此GmSSL可以替代应用中的OpenSSL组件,并使应用自动具备基于国密的安全能力。GmSSL项目采用对商业应用友好的类BSD开源许可证,开源且可以用于闭源的商业应用。

现成功移植GmSSL到i.MX平台,并且利用i.MX的加解密模块CAAM加速了SM2/SM9的运算。此外,还支持RSA,ECDSA/ECDH和DSA/DH以及AES,DES,SHA,MD5的硬件加速。

软件环境如下:

Linux kernel: imx_4.14.98_2.0.0_ga

cryptodev: 1.9

硬件平台: i.MX6UL, i.MX7D/S, i.MX8M/MM, i.MX8QM/QXP.

patch可以从下面的链接得到:

https://community.nxp.com/docs/DOC-343823

 

GmSSL官网链接http://gmssl.org/ 

watch

The way in which people digest information is changing, as more distractions lead way to shorter attention spans and multi-tasking becomes even more important.  The new training series from NXP, i.MX RT Tech Minute, is intended to address this.  The need for technical information present in things like webinars, applications notes, white papers, etc. is important.  But what if you do not even know which topic you are interested in?  How do you know where to get started?

The i.MX RT Tech Minute provides 1-2 minute intro videos about key topics that engineers are interested in.  Things like motor control, security, memory expansion – even PCB layout.  The links from the webpage, will then also direct you to where to find more information.  This way, engineers can dig deeper in to the topics that are most important to them. 

So, if you have a minute to spare, please check out the i.MX RT Tech Minute and see what areas you might want to dig deeper into.

nxp.com/iMXRTTechMinute

Have an idea for a future Tech Minute topic?  Comment below

i.MX RT LQFP Chip

As a marketer, I never like to use the suffix “less” as it usually has a negative connotation.  “Less” means not having; without; free from something. Words like hopeless, motionless, and helpless come to mind.  So, when a system architect recently spoke to me about the products in the i.MX RT series and referred to them as being flashless, I cringed a little.

 

But, is being flashless such a bad thing?  Yes, it means it has no flash memory on-chip, but that is actually giving customers more - More opportunity for differentiated on-chip peripherals.  More options for selecting the perfect memory.  And more opportunity to create cost competitive solutions.

 

More on-chip peripherals - Flash takes up a lot of die space on the MCU. By eliminating the flash, there is suddenly room for more differentiated features and peripherals. The i.MX RT series, for example, includes things like an advanced 2D graphics acceleration engine, LCD display controllers, camera sensor interfaces, and audio interfaces for high-performance, multi-channel audio streaming. And removing the flash allows the chip manufacturers to move to future technology nodes faster – thereby offering designers more peripherals and features in the same die space.

 

More flexibility to find the perfect memory - Because the i.MX RT series eliminates the flash, suddenly a whole world of memory options are available to designers.  i.MX RT series of crossover processors support greater design flexibility through extensive external memory interface options, including NAND, eMMC, Quad/Octal/Hyper SPI NOR Flash, and Parallel NOR Flash. The combination of high-speed interfaces for external memory and on-the-fly decryption enables secure external data storage, and the need for embedded flash is eliminated.  And sourcing external flash memory is easy and low-cost. By doing a quick search online, designers will see that 2MB of quad-SPI flash is only a couple of dollars.

 

More competitive - Embedding flash in an MCU is expensive.  Shedding the burden of on-chip flash reduces the MCU cost to the OEM and also helps enable higher frequency operation for increased processor performance—which in turn lets product designers boost capabilities, increase efficiency, and add more features.

 

The i.MX RT1015 is the newest addition to the popular i.MX RT Series and provides a great entry-point into the crossover processor space by providing a 500 MHz ARM Cortex-M7 core in a small LQFP package that enables 2-layer PCBs.  With 128 KB SRAM, the i.MX RT1015 supports external Flash memory options, and the EVK for the i.MX RT1015 features a Quad interface with Adesto’s 128Mbit, 133MHz Quad flash memory on-board.

 

i.MX RT1015 EVK

 

To learn more about i.MX RT, check out the i.MX RT fact sheet or visit http://www.nxp.com/iMXRT.